The fourth stage of special ceramics (1985-1992). This is the era of 32-bit microprocessors, and the representative product is the Intel 80386. Already capable of multi-tasking, multi-user jobs.
The 80486 processor released in 1989 realized a 5-stage scalar pipeline, marking the initial maturity of the CPU and the end of the traditional processor development stage. The fifth stage (1993-2005). This is the era Ceramic Tubes of the Pentium family of microprocessors. In November 1995, Intel released the Pentium processor, which for the first time adopted the superscalar instruction pipeline structure, introduced out-of-order execution of instructions and branch prediction technology, and greatly improved the performance of the processor. Therefore, the superscalar instruction pipeline structure It has been adopted by subsequent modern processors, such as AMD's (Advanced Micro devices) Ryzen and Intel's Core series. Phase VI (2005-2021). Processors are gradually developing towards more cores and higher parallelism. Typical representatives are Intel's Core series processors and AMD's Ryzen series processors. In order to meet the upper-layer work requirements of the operating system, modern processors further introduce functions such as parallelization, multi-core, virtualization, and remote management systems, which continuously promote the development of upper-layer information systems. The Von Neumann Ceramic Tubes architecture is the foundation of modern computers. Under this architecture, programs and data are stored in a unified manner, and instructions and data need to be accessed from the same storage space and transmitted through the same bus, and cannot be executed overlappingly. According to the von Neumann system, the work of the CPU is divided into the following five stages: instruction fetch stage, instruction decoding stage, instruction execution stage, access data and result write back. Instruction fetch (IF, instruction fetch) is the process of fetching an instruction from main memory to the instruction register. The value in the program counter that indicates the location of the current instruction in main memory. When an instruction is fetched, the value in the Program Counter (PC) will automatically increment according to the length of the instruction word. The instruction decoding stage (ID, instruction decode), after the instruction is fetched, the Ceramic Tubes instruction decoder splits and interprets the fetched instruction according to the predetermined instruction format, and identifies and distinguishes different instruction categories and various types of fetched operands. method. Modern CISC processors will split to improve parallelism and efficiency. Execute the instruction stage (EX, execute), which specifically implements the function of the instruction. Different parts of the CPU are connected to perform the required operations. In the access data stage (MEM, memory), according to the instruction needs to access the main memory, read the operand, the CPU obtains the address of the operand in the main memory, and reads the operand from the main memory for operation. Some instructions do not require access to main memory, so this stage can be skipped.
What is the sintering temperature of special ceramics?
2022 04/07